(1) Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data.
(2) Description of the Related Art
With semiconductor memory devices of a dynamic random access memory (DRAM) type including capacitors for accumulating electric charges and transistors for inputting data to and outputting data from them, refresh operation must be performed regularly to compensate for the leakage of electric charges from the capacitors. In such DRAM type semiconductor memory devices an electric current consumed at this refresh operation time will occupy a good part of an electric current consumed when they do not operate (when an operation is not performed from the outside and they are in an inactive state). Japanese Patent Laid-Open Publication No. 2001-143463 discloses accumulating electric charges by a twin storage system as an effective means of decreasing such a refresh current.
In this disclosure data to be stored is stored as complementary data in a pair of memory cells (hereinafter simply referred to as a cell) and the pair of memory cells are connected to a pair of bit lines connected to a common sense amplifier in response to the selection of a word line. That is to say, a pair of cells are located at the positions where a pair of bit lines connected to a sense amplifier and a word line intersect, and complementary data is written from the pair of bit lines to the pair of cells or is read out to the pair of bit lines by selecting the word line. “H” and “L” levels are stored in a pair of cells for 1-bit stored data. As a result, reading sensitivity improves and a refresh cycle can be lengthened significantly. Therefore, the amount of storage increases twofold, but an electric current consumed when DRAM type semiconductor memory devices do not operate can be decreased by reducing the number of times refresh operation is performed.
FIG. 28 is a view showing the concrete structure of a conventional twin-storage system semiconductor memory device. As shown in FIG. 28, a conventional twin-storage system semiconductor memory device comprises a row address pre-decoder 10, a main word decoder 11, an address pre-decoder 12, subword decoders #1 through #4, sense amplifiers 13-1 through 13-4, word lines WL1 through WL6, bit lines BL1 through BL8, and a cell array 14.
The row address pre-decoder 10 is a processing section at a stage just before them a in word decoder 11. The row address pre-decoder 10 inputs and decodes a row address, being an address in a row direction, and supplies a decode result to the main word decoder 11.
The main word decoder 11 further decodes a decode result supplied from the row address pre-decoder 10 and supplies a decode result to the subword decoders #1 through #4.
The address pre-decoder 12 accepts an input row address and supplies a result obtained by decoding it to the subword decoders #1 through #4. Moreover, at test operation time the address pre-decoder 12 accepts an input predetermined signal indicative of test operation.
The subword decoders #1 through #4 control the word lines WL2 through WL5, respectively, on the basis of decode results supplied from the main word decoder 11 and address pre-decoder 12.
The sense amplifiers 13-1 through 13-4 amplify data read from a cell included in the cell array 14.
As shown in FIG. 29, the cell array 14 includes a plurality of cell units C11 through C82 described later.
FIG. 30 is a view showing the detailed structure of the cell units C11 through C82 shown in FIG. 29. As shown in FIG. 30, a cell unit includes cells 30 and 31, gates 32 and 33, and a contact 34.
The cells 30 and 31 are basic units for recording data and hold bit information.
The gates 32 and 33 are connected to the word lines WL1 and WL2 respectively. The gate 32 connects the cell 30 and bit line BL2 according to voltage applied to the word line WL1 and the gate 33 connects the cell 31 and bit line BL2 according to voltage applied to the word line WL2.
The contact 34 supplies data read from the cell 30 or 31 to the bit line BL2 and supplies data applied to the bit line BL2 to the cell 30 or 31.
Now, operation in the above conventional twin-storage system semiconductor memory device will be described in brief with reading operation as an example.
When a row address is input, the word line WL3 will be activated if the subword decoder #2, for example, is selected by the operation of the row address pre-decoder 10, main word decoder 11, and address pre-decoder 12.
When the word line WL3 is activated, voltage will be applied to gates for controlling the upper cells in the cell units C11, C31, C51, and C71 and bit signals stored in these cells are read out.
The bit signals read out from these cells are supplied to the bit lines BL1, BL3, BL5, and BL7 respectively. The bit signals output to the bit lines BL1 and BL3 are supplied to the sense amplifier 13-1 and the bit signals output to the bit lines BL5 and BL7 are supplied to the sense amplifier 13-2. The bit lines BL1 and BL3 are used for sending ordinary data and auxiliary data respectively, so the logic of the bit signal output to the bit line BL1 is reverse to that of the bit signal output to the bit line BL3. The bit lines BL5 and BL7 are also used for sending ordinary data and auxiliary data respectively, so the logic of the bit signal output to the bit line BL5 is reverse to that of the bit signal output to the bit line BL7.
The sense amplifier 13-1 amplifies the signals output from the bit lines BL1 and BL3, specifies stored data by referring to amplified signals, and outputs specified results.
Similarly, the sense amplifier 13-2 amplifies the signals output from the bit lines BL5 and BL7, specifies stored data by referring to amplified signals, and outputs specified results.
With this system, a refresh cycle can be lengthened only if not only a cell which connects with a bit line (BL1, BL2, BL5, or BL6) for transmitting ordinary data but also a cell which connects with an auxiliary bit line (BL3, BL4, BL7, or BL8) for transmitting auxiliary data has no defect and can accumulate electric charges. However, there are cases where one cell cannot accumulate electric charges due to a defect and where the other cell can accumulate electric charges. In these cases, as a result of an operation test a pair of cells may appear to operate normally.
In that case, however, only one cell accumulates electric charges, so the refresh capability is much the same with a single storage cell. A refresh cycle for a device is set to cells of all the cells which have bad refresh characteristics. Therefore, if a pair of cells in which only one cell operates exist in a device, a refresh cycle must be shortened to them. As a result, the effect of lengthening a refresh cycle by adopting a twin storage system cannot be obtained.